Facebook FPGA Design Engineer in Topeka, Kansas
Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.
As the FPGA Design Engineer, you will be working within the FRL FPGA development team to build advanced AR/VR rapid prototyping platforms. You will be responsible for the architecture, RTL design, simulation, verification and test/bringup of FPGA's to meet end-to-end system requirements. This will require communicating and collaborating across functional teams to gather performance targets and use cases in order to build the right system solution. You will work closely with the systems integration and FW/SW teams for test/bringup/debug and will assist with system characterization and control/algorithm refinement. FPGA design work will require knowledge of and familiarity with all stages of the FPGA design process including simulation, floor planning, timing closure, and in-system debugging. Knowledge of Xilinx or Altera FPGA parts, their toolchains and architectural features is required.
RTL development and testing for FPGA targets/platforms to support rapid prototyping
Direct contingent/contract design and test resources
Assist with algorithm analysis, verification and improvement
Collaborate in a team environment across multiple engineering disciplines
Develop component and system level performance specifications
5+ years of FPGA design experience with Xilinx FPGA parts and Vivado design tools
Experience with at least 1 hardware description language (VHDL, Verilog, SystemVerilog)
Experience with commercial HDL simulators (Xcelium/Incisive, Modelsim/Questa, VCS, or Riviera)
Experience with board level testing (oscilloscope, logic analyzer)
BS Electrical Engineering (EE), Computer Engineering (CE) or Computer Science (CS) or equivalent experience
10+ years of FPGA design experience with Xilinx FPGA parts and Vivado design tools
Experience with System Verilog and coding skills
Experience with verification environments/methodologies
Experience with streaming video protocols (MIPI, AXI-Stream, etc.)
Experience with memory mapped bus interfaces (PCIe, AXI4-Stream, AHB, etc.)
Experience with FPGA emulation platforms (HAPS, ZeBu, etc.)
Experience with C/C++
Experience with both Windows and Linux environments
Experience with scripting in TCL and Python
Master’s degree in EE, CE or CS or equivalent experience
Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at email@example.com.